Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-6 Freescale Semiconductor
Table 11-2. eSDHC Memory Map
eSDHC Registers—Block Base Address 0x2_E000
Offset Register Access Reset Section/Page
0x000 DMA system address (DSADDR) R/W 0x0000_0000 11.4.1/11-7
0x004 Block attributes (BLKATTR) R/W 0x0001_0000 11.4.2/11-7
0x008 Command argument (CMDARG) R/W 0x0000_0000 11.4.3/11-8
0x00C Command transfer type (XFERTYP) R/W 0x0000_0000 11.4.4/11-9
0x010 Command response0 (CMDRSP0) R 0x0000_0000 11.4.5/11-12
0x014 Command response1 (CMDRSP1) R 0x0000_0000 11.4.5/11-12
0x018 Command response2 (CMDRSP2) R 0x0000_0000 11.4.5/11-12
0x01C Command response3 (CMDRSP3) R 0x0000_0000 11.4.5/11-12
0x020 Data buffer access port (DATPORT) R/W 0x0000_0000 11.4.6/11-14
0x024 Present state (PRSSTAT) R 0x0F80_00F8 11.4.7/11-15
0x028 Protocol control (PROCTL) R/W 0x0000_0020 11.4.8/11-19
0x02C System control (SYSCTL) Mixed 0x0000_8008 11.4.9/11-22
0x030 Interrupt status (IRQSTAT) w1c 0x0000_0000 11.4.10/11-24
0x034 Interrupt status enable (IRQSTATEN) R/W 0x117F_013F 11.4.11/11-28
0x038 Interrupt signal enable (IRQSIGEN) R/W 0x0000_0000 11.4.12/11-31
0x03C Auto CMD12 status (AUTOC12ERR) R 0x0000_0000 11.4.13/11-33
0x040 Host controller capabilities (HOSTCAPBLT) R 0x01F3_0000 11.4.14/11-35
0x044
1
1
The addresses following 0x044, except 0x050, 0x0FC and 0x40C, are reserved and read as all 0s. Writes to these registers
are ignored.
NOTE
For details on programming the CSB/eSDHC interface, see
Section 5.2.2.12, “eSDHC Control Registers (SDHCCR).”
Watermark level (WML) R/W 0x1010_1010 11.4.15/11-36
0x050 Force event (FEVT) W 0x0000_0000 11.4.16/11-36
0x0FC Host controller version (HOSTVER) R 0x0000_1201 11.4.17/11-38
0x40C DMA control register (DCR) R/W 0x0000_0000 11.4.18/11-38