Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-3
Figure 11-2 is a block diagram of the eSDHC.
Figure 11-2. eSDHC Block Diagram
11.2 Features
The eSDHC includes the following features:
• Compatible with the following specifications:
— SD Host Controller Standard Specification, Version 2.0 (http://www.sdcard.org) with test event
register support
— MultiMedia Card System Specification, Version 4.0 (http://www.mmca.org)
— SD Memory Card Specification, Version 2.0 (http://www.sdcard.org)
— SD Specifications, Part 1, Physical Layer Specification, Version 2.0
CMD/
channel
Tx/Rx
handler
Logic
CMD
CRC
Configurable
R/W
Embedded
CRC
Clock controller & divider
control
channel
state
machine
128- x 32-bit
buffer
controller
DMA
Register
Register
bank
Internal
dual-port
buffer
RAM
Logic
control
Data
channel
state
machine
CSB
master
port
Status register
interrupt
controller
Clock & reset
manager
SD bus
monitor
&
gating
eSDHC
Interrupt
bus
interface
Register
controller
clock
SD_CLK
SD
_CD
SD_WP
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
SD_CMD
bus