Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-101
The UPM also supports single beat accesses. Because the ZBT SRAM does not support this and always
responds with a burst, the UPM pattern has to take care that data for the critical beat is provided (for write)
or sampled (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller
basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities.
If a UPM device has OE, it should not be asserted in the same RAM word as the TA signal. If OE and TA
are both asserted in the same RAM word, then the eLBC may not be able to sample the correct data during
reads. Therefore OE must be asserted earlier than TA.