Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-100 Freescale Semiconductor
10.5.5 Interfacing to ZBT SRAM Using UPM
ZBT SRAMs have been designed to optimize the performance of table access in networking applications.
This section describes how to interface to ZBT SRAMs. Figure 10-77 shows the connections. The UPM
is used to generate control signals. The same interfacing is used for pipelined and flow-through versions
of ZBT SRAMs. However different UPM patterns must be generated for those cases. ZBT SRAMs are
mostly used by performance-critical applications, therefore, it is assumed that, typically, the maximum
width of the local bus of 16 bits will be used.
Figure 10-77. Interface to ZBT SRAM
ZBT SRAMs allow different configurations. For the local bus, the burst order should be set to linear burst
order by tying the mode pin to GND. CKE should also be tied to ground.
ZBT SRAMs perform four-beat bursts. Because the eLBC generates sixteen-beat transactions (for 16-bit
ports) the UPM breaks down each burst into four consecutive four-beat bursts. The internal address
generator of the eLBC generates the new {A21, A22} for the second, third, and fourth burst. In other
words, because linear burst is used on the SRAM, the device itself bursts with the burst addresses of
[0:1:2:3]. The local bus always generates linear bursts and expects [0:1:2:3:4:5:6:7:...:15]. Therefore, four
consecutive linear bursts of the ZBT SRAM with {A21, A22} = {0,0} for the first burst, {A21,
A22} = {0,1} for the second burst, {A21, A22} = {1,0} for the third burst, and {A21, A22} = {1,1} for
the fourth burst give the desired burst pattern.
DATA[0:15]
BW[0:1]
CE
1M  18
ADV/LD
WE
ZZ
BW[0:1]
MODE
CKE
CLK
SA[19:0]
ZBT
DQ[0:17]
OE
SRAM
LBS[0:1]
LCSn
LGPL0
LGPL2
LD[0:15]
LGPL1
Local Bus Interface
GPIO
LAn
LCLK