Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-97
Figure 10-75 shows refresh cycle (CBR) to FPM DRAM.
Figure 10-75. Refresh Cycle (CBR) to FPM DRAM
Table 10-53 lists UPM code for refresh cycle.
Table 10-53. UPM Code for Refresh Cycle
cst1 1 0 0 Bit 0
cst2 1 0 0 Bit 1
cst3 1 0 1 Bit 2
cst4 1 0 1 Bit 3
bst1 1 0 0 Bit 4
bst2 0 0 0 Bit 5
bst3 0 0 1 Bit 6
bst4 0 0 1 Bit 7
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t1 Bit 12
g1t3 Bit 13
g2t1 Bit 14
g2t3 Bit 15
LCLK
LD
LCS
n
LBCTL
A
LA
TA
(RAS)
LBSn
(CAS)