Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-93
Figure 10-73 shows single-beat write access to FPM DRAM.
Figure 10-73. Single-Beat Write Access to FPM DRAM
Table 10-51 lists UPM code for single-beat write access.
Table 10-51. UPM Code for Single-Beat Write Access
cst1 0 LA Pause
(due to change
in AMX)
00Bit 0
cst2 0 0 0 Bit 1
cst3 0 0 0 Bit 2
cst4 0 0 1 Bit 3
bst1 1 1 0 Bit 4
bst2 1 1 0 Bit 5
bst3 1 0 0 Bit 6
bst4 1 0 1 Bit 7
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t1 0 0 0 Bit 12
g1t3 0 0 0 Bit 13
LCLK
LD
LCS
n
LGPL1
A Row
LA
Column
Write Data
TA
Row lsb’s
Column lsb’s
(RAS)
LBSn
(CAS)
Write Data
LBCTL
(R/W)