Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-91
Figure 10-72 shows single-beat read access to FPM DRAM.
Figure 10-72. Single-Beat Read Access to FPM DRAM
Table 10-50 lists UPM code for single-beat read access.
Table 10-50. UPM Code for Single-Beat Read Access
cst1 0 LA Pause
(due to change
in AMX)
00Bit 0
cst2 0 0 0 Bit 1
cst3 0 0 0 Bit 2
cst4 0 0 0 Bit 3
bst1 1 1 0 Bit 4
bst2 1 0 0 Bit 5
bst3 1 0 0 Bit 6
bst4 1 0 0 Bit 7
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t1 1 1 1 Bit 12
g1t3 1 1 1 Bit 13
LCLK
LD
LCSn
LGPL1
A Row
LA
Read Data
Column
TA
Row lsb’s
Column lsb’s
(RAS)
LBSn
(CAS)
LBCTL
(R/W)