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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 473 (19x19) MPC83xx 32-Bit Single-Core 333 MHz

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Enhanced Local Bus Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

10-88 Freescale Semiconductor

10.5.3.4 NAND Flash Page Read Command Sequence Example

An example of configuring FCM to execute a random page read command to large-page NAND Flash is

shown in Table 10-47. This sequence reads an entire page (main and spare region) into the shared FCM

buffer RAM, checking ECC as it proceeds. The sequence is initiated by writing FMR[OP] = 11, and

issuing a special operation to the bank. A few cycles before completion itself, FECCn gets updated with

the ECC bytes for the main region validated by FECCn[0]. At the conclusion of the sequence, eLBC will

issue a command complete interrupt (LTESR[CC]) if interrupts are enabled. Once the sequence has

completed, the shared buffer (buffer 1 for page index 5) and transfer error registers (LTECCR that reports

the 512 blocks with unibit /multibit errors if any) are valid.

10.5.3.5 NAND Flash Block Erase Command Sequence Example

An example of configuring FCM to execute a block erase command to large-page NAND Flash is shown

in Table 10-48. This sequence does not require use of the shared FCM buffer RAM, but returns with the

erase status in MDR[AS0]. The sequence is initiated by writing FMR[OP] = 11, and issuing a special

MDR 0x00000000 AS0 = 0x00 = dummy address for read ID command;

AS0–AS3 return with first 4 bytes of ID code

FIR 0x43BBBBB0 OP0 = CM0 = command 0;

OP1 = UA = user address from MDR;

OP2–OP6 = RS = read 4 bytes ID into MDR[AS3–AS0];

OP7 = NOP

Table 10-47. FCM Register Settings for Page Read (ORn[PGS] = 1)

FCR 0x00300000 CMD0 = 0x00 = random read address entry;

CMD1 = 0x30 = read page

FBAR block index

(for example, block

0x00010ab4)

BLK locates index of 128-Kbyte block

FPAR page offset

(for example,

0x00005000 locates

page 5, buffer 1)

PI locates page index in BLK;

PI mod 2 indexes FCM buffer RAM;

MS = 0 and CI = 0

FBCR 0x00000000 BC = 0 to read entire 2112-byte page with ECC check

MDR — unused

FIR 0x4125E000 OP0 = CM0 = command 0;

OP1 = CA = column address;

OP2 = PA = page address;

OP3 = CM1 = command 1;

OP4 = RBW = wait on Flash ready and read data into FCM buffer;

OP5–OP7 = NOP

Table 10-46. FCM Register Settings for ID Read (ORn[PGS] = 1) (continued)