Information

Enhanced Local Bus Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 10-87

10.5.3.2 NAND Flash Read Status Command Sequence Example

An example of configuring FCM to execute a status read command to large-page NAND Flash is shown

in Table 10-45. This sequence does not require use of the shared FCM buffer RAM, but reads the NAND

Flash status into register MDR[AS0]. The sequence is initiated by writing FMR[OP] = 10 and issuing a

special operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete

interrupt (LTESR[CC]) if interrupts are enabled.

10.5.3.3 NAND Flash Read Identification Command Sequence Example

An example of configuring FCM to execute a status ID command to large-page NAND Flash is shown in

Table 10-46. This sequence does not require use of the shared FCM buffer RAM, but uses MDR to set up

a dummy address prior to the sequence, and then to receive the first 4 bytes of ID during the sequence. The

sequence is initiated by writing FMR[OP] = 10, and issuing a special operation to the bank. At the

conclusion of the sequence, eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are

enabled. MDR[AS3–AS0] then can be read to obtain the first 4 bytes of NAND Flash ID.

MDR — unused

FIR 0x40000000 OP0 = CM0 = command 0;

OP1–OP7 = NOP

Table 10-45. FCM Register Settings for Status Read (ORn[PGS] = 1)

FCR 0x70000000 CMD0 = 0x70 = read status command; other commands unused

FBAR — unused

FPAR — unused

FBCR — unused

MDR — Status returned in AS0

FIR 0x4B000000 OP0 = CM0 = command 0;

OP1 = RS = read status to MDR;

OP2–OP7 = NOP

Table 10-46. FCM Register Settings for ID Read (ORn[PGS] = 1)

FCR 0x90000000 CMD0 = 0x90 = read ID command; other commands unused

FBAR — unused

FPAR — unused

FBCR — unused

Table 10-44. FCM Register Settings for Soft Reset (ORn[PGS] = 1) (continued)