Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-84 Freescale Semiconductor
10.4.4.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose
some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the
slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to
any existing bus turnaround cycle.
10.5 Initialization/Application Information
10.5.1 Interfacing to Peripherals in Different Address Modes
This section provides guidelines for interfacing to peripherals.
10.5.1.1 GPCM Timings
In case a system contains a memory hierarchy with high speed synchronous memories (synchronous
SRAM) and lower speed asynchronous memories (for example, FLASH EPROM and peripherals) the
GPCM-controlled memories should be decoupled by buffers to reduce capacitive loading on the bus.
Those buffers have to be taken into account for the timing calculations.
Figure 10-69. GPCM Address Timings
To calculate address setup timing for a slower peripheral/memory device, the address setup for the actual
peripheral needs to be added.
For data timings, only the propagation delay of one buffer plus the actual data setup time has to be
considered.
Figure 10-70. GPCM Data Timings
A
Address
Slower
Memories
and
Peripherals
Device
Input
A
Pin
Local Bus Interface
LA[0:25]
Buffered Data
LBCTL
Local Bus Interface
Buffer
Slower
Memories
and
Peripherals
Device
Input
D
Pin
LD[0:15]