Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xlvi Freescale Semiconductor
Tables
Table
Number Title
Page
Number
13-47 Endpoint and Transaction Translator Characteristics ......................................................... 13-53
13-48 Microframe Schedule Control............................................................................................. 13-53
13-49 siTD Transfer Status and Control........................................................................................ 13-54
13-50 siTD Buffer Pointer Page 0 (Plus) ...................................................................................... 13-55
13-51 siTD Buffer Pointer Page 1 (Plus) ...................................................................................... 13-55
13-52 siTD Back Link Pointer ...................................................................................................... 13-55
13-53 qTD Next Element Transfer Pointer (DWord 0)................................................................. 13-57
13-54 qTD Alternate Next Element Transfer Pointer (DWord 1)................................................. 13-57
13-55 qTD Token (DWord 2)........................................................................................................ 13-58
13-56 qTD Buffer Pointer ............................................................................................................. 13-61
13-57 Queue Head DWord 0......................................................................................................... 13-62
13-58 Endpoint Characteristics: Queue Head DWord 1................................................................ 13-63
13-59 Endpoint Capabilities: Queue Head DWord 2 .................................................................... 13-64
13-60 Current qTD Link Pointer................................................................................................... 13-65
13-61 Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) ................................... 13-66
13-62 FTSN Normal Path Pointer................................................................................................. 13-67
13-63 FSTN Back Path Link Pointer ............................................................................................ 13-67
13-64 Behavior During Wake-Up Events...................................................................................... 13-71
13-65 Operation of FRINDEX and SOFV (SOF Value Register)................................................. 13-75
13-66 Example Periodic Reference Patterns for Interrupt Transfers ............................................ 13-88
13-67 Ping Control State Transition Table.................................................................................... 13-89
13-68 Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 13-103
13-69 Initial Conditions for OUT siTD TP and T-Count Fields ................................................. 13-112
13-70 Transaction Position (TP)/Transaction Count (T-Count) Transition Table....................... 13-112
13-71 Summary siTD Split Transaction State............................................................................. 13-116
13-72 Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 13-117
13-73 Summary of Transaction Errors........................................................................................ 13-120
13-74 Summary Behavior on Host System Errors ...................................................................... 13-123
13-75 Endpoint Capabilities/Characteristics............................................................................... 13-125
13-76 Current dTD Pointer.......................................................................................................... 13-126
13-77 Multiple Mode Control ..................................................................................................... 13-127
13-78 Next dTD Pointer.............................................................................................................. 13-127
13-79 dTD Token ........................................................................................................................ 13-128
13-80 Buffer Pointer Page 0........................................................................................................ 13-128
13-81 Buffer Pointer Page 1........................................................................................................ 13-129
13-82 Buffer Pointer Pages 2–4 .................................................................................................. 13-129
13-83 Device Controller State Information Bits ......................................................................... 13-131
13-84 Device Controller Endpoint Initialization......................................................................... 13-134
13-85 Device Controller Stall Response Matrix ......................................................................... 13-135
13-86 Variable Length Transfer Protocol Example (ZLT = 0).................................................... 13-137
13-87 Variable Length Transfer Protocol Example (ZLT = 1).................................................... 13-137