Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-83
Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to
complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is frozen until
LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
Figure 10-68 shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal are used
to hold the UPM in a particular state until LUPWAIT is negated. As the example shows, the LCSn and
LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as negated. WAEN is
typically set before the line that contains UTA = 1. Note that if WAEN and NA are both set in the same
RAM word, NA causes the burst address to increment once as normal regardless of whether the UPM
freezes.
Figure 10-68. Effect of LUPWAIT Signal
10.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any time, no
UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.
However, programming WAEN = 1 and UTA = 1 in the same RAM word allows the UPM to treat
LUPWAIT as a synchronous signal, which must meet set-up and hold times in relation to the rising edge
of the bus clock. In this mode, as soon as UPM samples LUPWAIT negated on the rising edge of the bus
clock, it immediately generates an internal transfer acknowledge, which allows a data transfer one bus
clock cycle later. The generation of transfer acknowledge is early because LUPWAIT is not
re-synchronized. The acknowledge occurs early or normally depending on whether the UPM was already
frozen inWAIT cycles or not. This feature allows the synchronous negation of LUPWAIT to affect a data
transfer, even if UTA, WAEN, and LAST are set simultaneously.
LCSn
LGPL1
WAEN
Word n Word n+1
c1
c2 c3 c4 c5 c6 c7 c8
LUPWAIT
c9 c10 c11 c12 c13 c14
Word n+2 Wait Word n+3
LCLK
T1
T2
T3
T4
A B
C
D
TA