Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-81
Table 10-42 shows how the RAM word AMX bits and MxMR[AM] settings can be used to affect
row × column address multiplexing on the LA[10:25] signals.
NOTE
Multiple-bank DRAM and SDRAM devices require that the bank address
be driven during both RAS and CAS cycles. The UPM does not support a
persistent bank address on both RAS and CAS cycles. Therefore, external
logic must be used to supply a bank address to these devices.
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the {LADn, LAn} bus with the assertion of LALE for the number of cycles set for LALE
in the ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
during the LALE phase.
NOTE
AMX must not change values in any RAM word which begins a loop.
Table 10-42. UPM Address Multiplexing
msb Internal Transaction Address lsb
0 1 2 3 4 5 6 7 8 9 1011121314151617181920 21 222324252627282930 31
AMX = 10
MxMR[AM] = 000
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LA
18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 001
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LA
17 18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 010
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LA
16 17 18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 011
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LAD LA
15 16 17 18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 100
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LAD LA
14 15 16 17 18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 101
(Row)
LAD LA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 00
(Col)
LAD LA
13 14 15 16 17 18 19 20 21 22 23 24 25
AMX = 10
MxMR[AM] = 110
Reserved
AMX = 10
MxMR[AM] = 111
Reserved