Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-78 Freescale Semiconductor
10.4.4.4.2 Chip-Select Signal Timing (CSTn)
If BRn[MSEL] of the accessed bank selects a UPM on the currently requested cycle, the UPM manipulates
the LCSn for that bank with timing as specified in the UPM RAM word CSTn fields. The selected UPM
affects only the assertion and negation of the appropriate LCSn signal. The state of the selected LCSn
signal of the corresponding bank depends on the value of each CSTn bit. Figure 10-65 shows how UPMs
control LCSn signals.
Figure 10-65. LCSn Signal Selection
10.4.4.4.3 Byte Select Signal Timing (BSTn)
If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected
UPM affects the assertion and negation of the appropriate LBS
[0:1] signal. The timing of both byte-select
signals is specified in the RAM word. However, LBS
[0:1] are also controlled by the port size of the
accessed bank, the number of bytes to transfer, and the address accessed. Figure 10-66 shows how UPMs
control LBS
[0:1].
31 LAST Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control
signal timing set in the RAM word is applied to the current (and last) cycle. However, if the
disable timer is activated and the next access is to the same bank, execution of the next UPM
pattern is held off and the control signal values specified in the last word are extended in
duration for the number of clock cycles specified in MxMR[DSn].
0 The UPM continues executing RAM words.
1 Indicates the last RAM word in the program. The service to the UPM request is done after
this cycle concludes.
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
Table 10-40. RAM Word Field Descriptions (continued)
Bits Name Description
UPMA/B/C
FCM
GPCM
MUX
BRn[MSEL]
LCS2
LCS3
Switch
Bank Selected
LCS0
LCS1