Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-75
Table 10-40 contains descriptions of the RAM word fields.
012 3 456789101112 13 1415
R
CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4 G0L G0H G1T1 G1T3 G2T1 G2T3
W
Reset All zeros
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
G3T1 G3T3
G4T1/
DLT3
G4T3/
WAEN
G5T1 G5T3 REDO LOOP EXEN AMX NA
UTA
TODT LAST
W
Reset All zeros
Figure 10-64. RAM Word Fields
Table 10-40. RAM Word Field Descriptions
Bits Name Description
0 CST1 Chip select timing 1. Defines the state (0 or 1) of LCS
n during bus clock quarter phase 1 if
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCSn during bus clock half phase 1 if
LCRR[CLKDIV] = 2.
1 CST2 Chip select timing 2. Defines the state (0 or 1) of LCSn during bus clock quarter phase 2 if
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
2 CST3 Chip select timing 3. Defines the state (0 or 1) of LCS
n during bus clock quarter phase 3 if
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCSn during bus clock half phase 2 if
LCRR[CLKDIV] = 2.
3 CST4 Chip select timing 4. Defines the state (0 or 1) of LCSn during bus clock quarter phase 4 if
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
4 BST1 Byte select timing1. Defines the state (0 or 1) of LBS
during bus clock quarter phase 1
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 1 (LCRR[CLKDIV] = 2), in conjunction with
BRn[PS] and LA[24:25].
5 BST2 Byte select timing 2. Defines the state (0 or 1) of LBS during bus clock quarter phase 2
(LCRR[CLKDIV] = 4 or 8), in conjunction with BRn[PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
6 BST3 Byte select timing 3. Defines the state (0 or 1) of LBS
during bus clock quarter phase 3
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 2 (LCRR[CLKDIV] = 2), in conjunction with
BRn[PS] and LA[24:25].
7 BST4 Byte select timing 4. Defines the state (0 or 1) of LBS
during bus clock quarter phase 4
(LCRR[CLKDIV] = 4 or 8), in conjunction with BRn[PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
8–9 G0L General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases
1 and 2 (first half phase).
00 Value defined by MxMR[G0CL]
01 Reserved
10 0
11 1