Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-72 Freescale Semiconductor
– Since the result of any update to the MxMR/MDR register must be in effect before the dummy
read or write to the UPM region, a write to MxMR/MDR should be followed immediately by a
read of MxMR/MDR.
– The UPM memory region should have the same MMU settings as the memory region containing
the MxMR configuration register; both should be mapped by the MMU as cache-inhibited and
guarded. This prevents the CPU from re-ordering a read of the UPM memory around the read of
MxMR. Once the programming of the UPM array is complete the MMU setting for the
associated address range can be set to the proper mode for normal operation, such as cacheable
and copyback.
For proper signalling, the following guidelines must be followed while programming UPM RAM words:
• For UPM reads, program UTA and LAST in the same or consecutive RAM words.
• For UPM burst reads, program last UTA and LAST in the same or consecutive RAM words.
• For UPM writes, program UTA and LAST in the same RAM word.
• For UPM burst writes, program last UTA and LAST in the same RAM word.
10.4.4.2.1 UPM Programming Example (Two Sequential Writes to the RAM Array)
The following example further illustrates the steps required to perform two writes to the RAM array at
non-sequential addresses assuming that the relevant BRn and ORn registers have been previously set up:
1. Program MxMR for the first write (with the desired RAM array address).
2. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
configuration.
3. Read MDR to ensure that the MDR has already been updated with the desired pattern. (Or, read
MxMR register if step 2 is not performed.)
4. Perform a dummy write transaction.
5. Read/check MxMR[MAD]. If incremented, the previous dummy write transaction is completed;
proceed to step 6. Repeat step 5 until incremented.
6. Program MxMR for the second write with the desired RAM array address.
7. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
configuration.
8. Read MDR to ensure that the MDR has already been updated with the desired pattern.
9. Perform a dummy write transaction.
10. Read/check MxMR[MAD]. If incremented, the previous dummy write transaction is completed.
Note that if step 1 (or 6) and 2 (or 7) are reversed, step 3 (or 8) is replaced by the following:
• Read MxMR to ensure that the MxMR has already been updated with the desired configuration.
10.4.4.2.2 UPM Programming Example (Two Sequential Reads from the RAM Array)
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (MxMR[OP] = 0b10). The following example further