Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-69
The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
10.4.4.1 UPM Requests
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device’s request for a memory access initiates one of the following patterns (MxMR[OP] = 00):
• Read single-beat pattern (RSS)
• Read burst cycle pattern (RBS)
• Write single-beat pattern (WSS)
• Write burst cycle pattern (WBS)
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is running
initiates an exception condition pattern (EXS).
Figure 10-59 and Table 10-39 show the start addresses of these patterns in the UPM RAM, according to
cycle type. RUN commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64
UPM RAM words.
Figure 10-59. RAM Array Indexing
Table 10-39. UPM Routines Start Addresses
UPM Routine Routine Start Address
Read single-beat (RSS) 0x00
Read burst (RBS) 0x08
Write single-beat (WSS) 0x18
Write burst (WBS) 0x20
Write Single-Beat Request
Read Burst Request
Read Single-Beat Request
Write Burst Request
RAM Array
Refresh Timer Request
Exception Condition Request
RSS
RBS
WSS
WBS
RTS
EXS
64 RAM
Words
Array Index
Generator