Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-68 Freescale Semiconductor
6. The CPU now commences fetching instructions, in random order, from the FCM buffer RAM. This
first-level boot loader typically copies a secondary boot loader into system memory, and continues
booting from there. Boot software must clear FMR[BOOT] to enable normal operation of FCM.
10.4.4 User-Programmable Machines (UPMs)
UPMs are flexible interfaces that connect to a wide range of memory devices. At the heart of each UPM
is an internal RAM array that specifies the logical value driven on the external memory control signals
(LCSn, LBS[0:1] and LGPL[0:5]) for a given clock cycle. Each word in the RAM array provides bits that
allow a memory access to be controlled with a resolution of up to one quarter of the external bus clock
period on the byte-select and chip-select lines. A gap of 2 dead LCLK cycles is present on the UPM
interface between UPM transactions.
NOTE
If the LGPL4/LGTA/LFRB/LUPWAIT signal is used as both an input and
an output, a weak pull-up is required. For details regarding termination
options, see MPC8308 PowerQUICC II Pro Processor Hardware
Specification.
Figure 10-58 shows the basic operation of each UPM.
Figure 10-58. User-Programmable Machine Functional Block Diagram
The following events initiate a UPM cycle:
• Any internal device requests an external memory access to an address space mapped to a
chip-select serviced by the UPM
• A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
• A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an
exception sequence
Run Command
UPM Refresh
Timer Request
Array
Index
Generator
Internal / External
Memory Access Request
Exception Request
Index
Signals
Timing
Generator
Internal
Signals
Latch
Wait
Request
Logic
RAM Array
LUPWAIT
WAEN Bit
Internal Controls
LGPLn
Increment
Index
(LAST = 0)
Hold
(issued in software)
LBS
n
LCSn