Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-66 Freescale Semiconductor
When the core begins accessing memory after system reset, LCS0 is asserted initially to load a 4-Kbyte
boot block into the FCM buffer RAM, but core instruction fetches occur from the buffer RAM.
10.4.3.4.1 FCM Bank 0 Reset Initialization
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset. Table 10-38 describes
the initial values of the boot bank in the memory controller.
10.4.3.4.2 Boot Block Loading into the FCM Buffer RAM
If FCM is selected as the boot ROM controller from power-on-reset configuration, eLBC will
automatically load from bank 0 a single 4 Kbyte page of boot code into the FCM buffer RAM during
HRESET (See Section 4.3.2.2.3, “Boot ROM Location.”). The CPU can execute boot code directly from
the FCM buffer RAM, but must ensure that any further data read from the NAND Flash EEPROM is
transferred under software control in order to continue the bootstrap process.
Since OR0[AM] is initially cleared during reset, all CPU fetches to eLBC will access the FCM buffer
RAM, which appears in the memory map as a 4-Kbyte RAM. No NAND Flash spare regions are mapped
during boot, therefore only 4 Kbytes of contiguous, main region data, loaded from the first pages of the
boot block, are accessible in eLBC bank 0, as indicated in Figure 10-57.
Table 10-38. Boot Bank Field Values after Reset for FCM as Boot Controller
Register Field Setting
BR0 BA
PS
DECC
WP
MSEL
V
0000_0000_0000_0000_0
01
From LB_POR_CFG_BOOT_ECC
0
001
1
OR0 AM
BCTLD
PGS
CSCT
CST
CHT
RST
SCY
TRLX
EHTR
0000_0000_0000_0000_0
0
From RCWH[ROMLOC], RLEXT = 01
1
1
1
1
010
1