Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-65
The timing parameters are summarized in Table 10-37.
10.4.3.3.5 FCM Extended Read Hold Timing
Allowance for slow output driver turn-off when reading NAND Flash EEPROMs is made via setting of
ORn[EHTR] and ORn[TRLX]. The extended read data hold time, shown at t
EHTR
in Figure 10-45 and
Figure 10-56, is a delay inserted by FCM between the last data read and another eLBC memory access.
LCSn is negated during t
EHTR
to allow external devices and bus transceivers time to disable their drivers.
Figure 10-56. FCM Read Data Timing with Extended Hold Time
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1, CLKDIV = 4*N)
10.4.3.4 FCM Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
Table 10-37. FCM Read Data Timing Parameters
Option Register
Attributes
Timing Parameter (LCLK Clock Cycles)
1
1
In the parameters, SCY refers to a delay of ORn[SCY] clock cycles.
TRLX RST t
RP
t
RHT
t
WS
t
RC
t
WRT
0 0 ¾+SCY 1 SCY 2+SCY 4×(2+SCY)
0 1 1+SCY 1 SCY 2+SCY 4×(2+SCY)
1 0 ½+2×SCY 2 2×SCY 3+2×SCY 8×(2+SCY)
1 1 1+2×SCY 2 2×SCY 3+2×SCY 8×(2+SCY)
LCLK
LFCLE/
LFALE
LFRE
LD[0:7]
TA
read cycle
t
RC
(unused)
t
RC
= Read data cycle time.Notes:
last read data
LCSn
t
EHTR
= Extended read data hold time.
LALE
(unused/internal)
t
EHTR