Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-64 Freescale Semiconductor
Figure 10-54. FCM Delay Prior to Sampling LFRB State
10.4.3.3.4 FCM Read Data Timing
The timing for read data transfers is shown in Figure 10-55. Upon assertion of LFRE, the Flash device will
enable its output drivers and drive valid read data while LFRE is held low. FCM samples read data on the
rising edge of LFRE, which follows an optional number of wait states. Note that FCM will delay the first
read if a RBW or RSW instruction is issued, in which case LFRB sample timing takes effect (see
Section 10.4.3.3.3, “FCM Ready/Busy Timing”).
Figure 10-55. FCM Read Data Timing
(for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N)
LFCLE
LFWE
LFRB
LFRE
8×(2+SCY) cycles
16×(2+SCY) LCLK cycles
TRLX = 0:
TRLX = 1:
FCM continues
following LFR
B high
long-latency CW command issue
LFR
B sample
points
ready state
NAND FlashFlash busy state
sample data
LCLK
LFCLE/
LFALE
LFRE
LD[0:7]
TA
read cycle
t
RHT
t
WS
t
RC
t
RP
(unused)
t
RHT
= LFRE hold time.
t
RP
= LFRE pulse time, read period. t
WS
= Read wait state time.
t
RC
= Read data cycle time.
Notes:
LFWE0
t
WRT
write-to-read turnaroundwrite cycle
write data read data
t
WRT
= Write to read turnaround time.