Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-63
Figure 10-52. Example of FCM Command and Address Timing with Minimum Delay Parameters
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)
An example of relaxed command timing is shown in Figure 10-53.
Figure 10-53. Example of FCM Command and Address Timing with Relaxed Parameters
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)
10.4.3.3.3 FCM Ready/Busy Timing
Instructions CW0, CW1, RBW, and RSW force FCM to observe the state of the LFRB pin, which may be
driven low by a long-latency NAND Flash operation, such as a page read. Following the issue of such
commands, FCM waits as shown in Figure 10-54 before sampling the state of LFRB
. This guards against
observing LFRB
before it has been properly driven low by the device, but does not preclude LFRB from
remaining high after a command. In addition, FCM samples and compares the state of LFRB
on two
consecutive cycles of LCLK to filter out noise on this signal as it rises to the ready state (LFRB = 1).
LCLK
LFCLE
LFALE
LFWE0
LD[0:7]
TA
(unused)
command address 0 address 1 address 2
LCLK
LFCLE
LFALE
LFWE0
LD[0:7]
TA
(unused)
command address
2×SCY = 4 cycles