Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-62 Freescale Semiconductor
Figure 10-51. Timing of FCM Command/Address and Write Data Cycles
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)
The timing parameters are summarized in Table 10-36.
An example of minimum delay command timing appears in Figure 10-52. Note that the set-up, wait-state,
and hold timing of command, address, and write data cycles with respect to LFWE0 assertion are all
identical, and that the minimum cycle extends for two LCLK clock cycles.
Table 10-36. FCM Command, Address, and Write Data Timing Parameters
Option Register Attributes Timing Parameter (LCLK Clock Cycles)
1
1
In the parameters, SCY refers to a delay of ORn[SCY] clock cycles.
TRLX CHT CST t
CST
t
CHT
t
WS
t
WP
t
WC
t
ADL
0 0 0 0 ½ SCY 1½+SCY 2+SCY 4×(2+SCY)
0 0 1 ¼ ½ SCY 1¼+SCY 2+SCY 4×(2+SCY)
0 1 0 0 1 SCY 1+SCY 2+SCY 4×(2+SCY)
0 1 1 ¼ 1 SCY ¾+SCY 2+SCY 4×(2+SCY)
1 0 0 ½ 1½ 2×SCY 1+2×SCY 3+2×SCY 8×(2+SCY)
1 0 1 1 1½ 2×SCY ½+2×SCY 3+2×SCY 8×(2+SCY)
1 1 0 ½ 2 2×SCY ½+2×SCY 3+2×SCY 8×(2+SCY)
1 1 1 1 2 2×SCY 2×SCY 3+2×SCY 8×(2+SCY)
LCLK
LFCLE/
LFALE
LFWE
0
LD[0:7]
TA
write cycle #1 write cycle #2
t
CST
t
CHT
t
WS
t
WC
t
WP
(unused)
t
CST
= Command to LFWE0 set-up time.
t
CHT
= Command to LFWE0 hold time.
t
WP
= LFWE0 pulse time, driven low.
t
WS
= Command wait state time.
t
WC
= Command cycle time.
Notes:
command/address
write data
t
ADL
t
ADL
= Command/address to write data delay.