Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-61
instruction. Sampling and time-outs for polling the LFRB pin follow the behavior of CWn
instructions.
10.4.3.2.5 FCM Data Write Instructions
Data write instructions assert LFWE0 repeatedly (with LFCLE and LFALE both negated) to transfer one
or more bytes of write data to the NAND Flash EEPROM. Data write instructions are distinguished by
their data source:
• Write data from FCM buffer RAM—WB. This instruction writes FBCR[BC] bytes of data from
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
stored in the appropriate FECCn registers and spare region in accordance with the setting of
FMR[ECCM]. If the value of FBCR[BC] takes the write pointer beyond the end of the spare region
in the buffer, the value of data written by FCM is undefined.
• Write data/status from MDR—WS. This instruction asserts LFWE0 exactly once to write one byte
(8-bit port size) of data taken from the next AS field of MDR. Attempts to write beyond four bytes
of MDR has the effect of writing zeros. The MDR write pointer is independent of the MDR read
pointer used by RS and RSW instructions.
10.4.3.3 FCM Signal Timing
If BRn[MSEL] selects the FCM, the attributes for the memory cycle are taken from ORn. These attributes
include the CSCT, CST, CHT, RST, SCY, TRLX, and EHTR fields.
10.4.3.3.1 FCM Chip-Select Timing
The timing of LCSn assertion in FCM mode is illustrated by the timing diagram in Figure 10-45. LCSn
remains asserted until the last instruction in FIR has completed. The delay, t
CSCT
, between LCSn assertion
and commencement of the first NAND Flash instruction is controlled by ORn[CSCT] and ORn[TRLX],
as shown in Table 10-35. ORn[CSCT] should be set in accordance with the NAND Flash EEPROM
chip-select to WE set-up time specification.
10.4.3.3.2 FCM Command, Address, and Write Data Timing
The FCM command (CM0–CM3, CW0, CW1), address (CA, PA, UA), and data write (WB, WS)
instructions all share the same basic timing attributes. Assertion of LFWE0 initiates transfer via LD[0:7],
and the options in ORn for FCM mode establish the set-up, hold, and wait state timings with respect to
LFWE0, as shown in Figure 10-51.
Table 10-35. FCM Chip-Select to First Command Timing
ORn[TRLX] ORn[CSCT] LCSn to First Command Delay
0 0 1 LCLK clock cycle
0 1 4 LCLK clock cycles
1 0 2 LCLK clock cycles
1 1 8 LCLK clock cycles