Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-60 Freescale Semiconductor
10.4.3.2.3 FCM Address Instructions
Address instructions are used to issue addresses to the NAND Flash EEPROM. A complete device address
is formed from a sequence of one or more bytes, each written onto LD[0:7] with LFALE and LFWE0
asserted together. There are three kinds of address generation provided:
• Column address—CA. A column address comprises one byte (ORn[PGS] = 0) or two bytes
(ORn[PGS] = 1) locating the starting byte or word to be transferred in the next page read or write
sequence. FPAR[CI] sets the value of the column index provided that FBCR[BC] is non-zero. In
the case that FBCR[BC] = 0, a column index of zero is issued to the device, regardless of the value
in FPAR[CI].
• Page address—PA. A page address comprises 2, 3, or 4 bytes, depending on the setting of
FMR[AL], and locates the data page in the NAND Flash address space. The complete page address
is the concatenation of the block index, read from FBAR[BLK], with the page-in-block index, read
from FPAR[PI]. The page address length set in FMR[AL] should correspond with the size of
EEPROM being accessed. Similarly, the block index in FBAR[BLK] must not exceed the
maximum block index for the device, as most devices require reserved address bits to be written
as zero.
• User-defined address—UA. This instruction allows the FCM to write a user-defined address byte,
which is read from the next AS field in MDR, starting at MDR[AS0]. Each subsequent UA
instruction reads an adjacent AS field in MDR, until all four AS bytes (MDR[AS0], MDR[AS1],
MDR[AS2], MDR[AS3]) have been sent; a fifth and any following UA instructions send zero as
the address byte. Note that each UA instruction advances the MDR pointer for writes by one byte,
and therefore a mix of UA and WS instructions can consume adjacent bytes from MDR.
10.4.3.2.4 FCM Data Read Instructions
Data read instructions assert LFRE repeatedly to transfer one or more bytes of read data from the NAND
Flash EEPROM. Data read instructions are distinguished by their data destination:
• Read data to buffer RAM immediately—RB. This instruction reads FBCR[BC] bytes of data into
the current FCM RAM buffer addressed by FPAR. If FBCR[BC] = 0, an entire page (including
spare region) is transferred in a burst, starting at the page boundary, and the ECC calculation is
checked against the ECC stored in the spare region. Correctable ECC errors are corrected and
reported in LTECCR[SBCE]; other errors may cause an interrupt if enabled. If the value of
FBCR[BC] takes the read pointer beyond the end of the spare region in the buffer, FCM discards
any excess bytes read.
• Read data/status to MDR immediately—RS. This instruction asserts LFRE
exactly once to read
one byte (8-bit port size) of data into the next AS field of MDR. Reads beyond the fourth byte of
MDR are discarded. The MDR read pointer is independent of the MDR write pointer used by UA
and WS instructions.
• Read data to buffer RAM once waited on ready—RBW. This instruction first polls the LFRB
pin,
waiting for it to go high, before proceeding with a read to buffer as described for the RB instruction.
Sampling and time-outs for polling the LFRB
pin follow the behavior of CWn instructions.
• Read data/status to MDR once waited on ready—RSW. This instruction first polls the LFRB
pin,
waiting for it to go high, before proceeding with a status read to MDR as described for the RS