Information
Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-59
Figure 10-50. FCM Instruction Sequencer Mechanism
10.4.3.2.1 FCM Command Instructions
There are two kinds of command instruction:
• Commands that issue immediately—CM0, CM1, CM2, and CM3. These commands write a single
command byte by asserting LFCLE and LFWE0 while driving an 8-bit command onto LD[0:7].
Op-code CMn sources its command byte from field FCR[CMDn], therefore up to four different
commands can be issued in any FCM instruction sequence.
• Commands that wait for LFRB to be sampled high (EEPROM in ready state) before
issuing—CW0, and CW1. These commands first poll the LFRB pin, waiting for it to go high,
before writing a single command byte onto LD[0:7], sourced from FCR[CMDn] for op-code CWn.
It is necessary to use CWn op-codes whenever the EEPROM is expected to be in a busy state (such
as following a page read, block erase, or program operation) and therefore initially unresponsive
to commands. To avoid deadlock in cases where the device is already available, FCM does not
expect a transition on LFRB
. Rather, FCM waits for 8 × (2 + ORn[SCY]) clock cycles (when
ORn[TRLX] = 0) or 16 × (2 + ORn[SCY]) clock cycles (when ORn[TRLX] = 1) before sampling
the level of LFRB. If the level of LFRB does not return high before a time-out set by FMR[CWTO]
occurs, FCM proceeds to issue the command normally, and a FCT event is issued to LTESR.
The manufacturer’s datasheet should be consulted to determine values for programming into the FCR
register, and whether a given command in the sequence is expected to initiate busy device behavior.
10.4.3.2.2 FCM No-Operation Instruction
A NOP instruction that appears in FIR ahead of the last instruction is executed with the timing of a regular
command instruction, but neither LFCLE nor LFWE0 are asserted. Thus a NOP instruction may be used
to insert a pause matching the time taken for a regular command write.
FIR Register
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
Flash instruction shift register
parallel load on FCM bank select
FCM Instruction
Buffer
FMR Register
FBAR Register
FPAR Register
MDR Register
FBCR Register
op-code data
NAND Flash
Bus Signal
Generator
LFWE0
LFCLE
LFALE
LFRE
LFRB
LFWP
4 bits 8 bits
FCR Register
4 bits
LD[0:7]
MDR AS select
NOP