Information

Enhanced Local Bus Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 10-57

starting address in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC

banks control both small and large-page devices, a large-page 4 Kbyte buffer must be assigned to either

the first 4 or last 4 small-page buffers.

Figure 10-47. FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND Flash Devices

10.4.3.1.3 Error Correcting Codes and the Spare Region

The FCM’s ECC engine makes use of data in the NAND Flash spare region to store pre-computed ECC

code words. ECC is calculated in a single pass over blocks of 512 bytes of data in the main region. The

setting of FMR[ECCM] determines the location of the 24-bit ECC in the spare region.

The basic ECC algorithm is depicted in Figure 10-48. The stream of data bytes is considered to form a

matrix having 8 columns (corresponding with the device bus IO[7:0] or IO[15:8]) and 512 rows

(corresponding with each byte in the ECC block).

Figure 10-48. FCM ECC Calculation

Bank Base Address

offset 0x1000

offset 0x2000

buffer #0/page 0

buffer #1/page 1

replicated FCM

buffer RAM

images in bank

4 Kbyte page buffer:

2048-byte main region (FPAR[MS] = 0)

64-byte spare region (FPAR[MS] = 1)

1984-byte reserved region (FPAR[MS] = 1)

End of Bank

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

byte 0

byte 1

byte 510

byte 511

ECC

block