Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-54 Freescale Semiconductor
Figure 10-44. Local Bus to 8-Bit FCM Device Interface
Basic read access timing for FCM is shown in Figure 10-45. Although LCLK is shown for reference,
NAND Flash EEPROMs do not make use of the clock.
Figure 10-45. FCM Basic Page Read Timing
(PGS = 1, CSCT = 0, CST = 0, CHT = 1, RST = 1, SCY = 0, TRLX = 0, EHTR = 1)
CE
IO[7:0]
8-bit
LFWE0
LCSn
LD[0:7]
eLBC in FCM
Mode
NAND Flash EEPROM
N.C.
N.C.
LFWP
WP
LFRB RDY/BSY
3.3V
LFRE
RE
WE
LFALE
LFCLE
ALE
CLE
4.7K
LD[8:15]
LA
LCLK
LCS
x
LFCLE
LFALE
LFWE0
LD[0:7]
LFRB
LFRE
CA PACMD0 CMD1
READY BUSY
D
0
D
1
D
2
D
3
D
2k-1
D
2k
TA
Read Data
(not used)
t
CSCT
CMD0 = 1st command
CMD1 = 2nd command
CA = column address
PA = page address
LBCTL