Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xliii
Tables
Table
Number Title
Page
Number
10-29 FPAR Field Descriptions, Large Page Device (ORx[PGS] = 1)......................................... 10-37
10-30 FBCR Field Descriptions.................................................................................................... 10-38
10-31 FECCn Field Descriptions .................................................................................................. 10-39
10-32 GPCM Read Control Signal Timing................................................................................... 10-44
10-33 GPCM Write Control Signal Timing .................................................................................. 10-45
10-34 Boot Bank Field Values after Reset for GPCM as Boot Controller.................................... 10-53
10-35 FCM Chip-Select to First Command Timing...................................................................... 10-61
10-36 FCM Command, Address, and Write Data Timing Parameters.......................................... 10-62
10-37 FCM Read Data Timing Parameters................................................................................... 10-65
10-38 Boot Bank Field Values after Reset for FCM as Boot Controller ...................................... 10-66
10-39 UPM Routines Start Addresses........................................................................................... 10-69
10-40 RAM Word Field Descriptions ........................................................................................... 10-75
10-41 MxMR Loop Field Use ....................................................................................................... 10-80
10-42 UPM Address Multiplexing................................................................................................ 10-81
10-43 Data Bus Drive Requirements For Read Cycles................................................................. 10-85
10-44 FCM Register Settings for Soft Reset (ORn[PGS] = 1) ..................................................... 10-86
10-45 FCM Register Settings for Status Read (ORn[PGS] = 1)................................................... 10-87
10-46 FCM Register Settings for ID Read (ORn[PGS] = 1) ........................................................ 10-87
10-47 FCM Register Settings for Page Read (ORn[PGS] = 1)..................................................... 10-88
10-48 FCM Register Settings for Block Erase (ORn[PGS] = 1) .................................................. 10-89
10-49 FCM Register Settings for Page Program (ORn[PGS] = 1) ............................................... 10-90
10-50 UPM Code for Single-Beat Read Access ........................................................................... 10-91
10-51 UPM Code for Single-Beat Write Access........................................................................... 10-93
10-52 UPM Code for Burst Read Access...................................................................................... 10-95
10-53 UPM Code for Refresh Cycle ............................................................................................. 10-97
10-54 UPM Code for Exception Cycle ......................................................................................... 10-99
11-1 Signal Properties ................................................................................................................... 11-5
11-2 eSDHC Memory Map........................................................................................................... 11-6
11-3 DSADDR Field Descriptions................................................................................................ 11-7
11-4 BLKATTR Field Descriptions .............................................................................................. 11-8
11-5 CMDARG Field Descriptions............................................................................................... 11-9
11-6 XFERTYP Field Descriptions............................................................................................... 11-9
11-7 Determination of Transfer Type...........................................................................................11-11
11-8 Relation Between Parameters and Name of Response Type .............................................. 11-12
11-9 Response Bit Definition for Each Response Type.............................................................. 11-13
11-10 DATPORT Field Descriptions ............................................................................................ 11-14
11-11 PRSSTAT Field Descriptions.............................................................................................. 11-15
11-12 PROCTL Field Descriptions............................................................................................... 11-19
11-13 SYSCTL Field Descriptions ............................................................................................... 11-22
11-14 IRQSTAT Field Descriptions .............................................................................................. 11-25
11-15 Relation Between Command Timeout Error and Command Complete Status................... 11-28