Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-53
10.4.3 Flash Control Machine (FCM)
The FCM provides a glueless interface to parallel-bus NAND Flash EEPROM devices. The FCM contains
three basic configuration register groups—BRn, ORn, and FMR.
Figure 10-44 shows a simple connection between an 8-bit port size NAND Flash EEPROM and the eLBC
in FCM mode. Commands, address bytes, and data are all transferred on LD[0:7]
1
, with LFWE0 asserted
for transfers written to the device, or LFRE asserted for transfers read from the device. eLBC signals
LFCLE and LFALE determine whether writes are of type command (only LFCLE asserted), address (only
LFALE asserted), or write data (neither LFCLE nor LFALE asserted). The NAND Flash RDY/BSY pin is
normally open-drain, and should be pulled high by a 4.7-K resistor. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0
) prior to the system being fully
configured.
Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller
Register Field Setting
BR0 BA 0000_0000_0000_0000_0
PS From RCWH[ROMLOC], RLEXT = 0
DECC 00
WP 0
MSEL 000
V1
OR0 AM 0000_0000_0000_0000_0
BCTLD 0
CSNT 1
ACS 11
XACS 1
SCY 1111
SETA 0
TRLX 1
EHTR 1
1. Note bit numbering reversal: LD[0] (msb) connects to Flash IO[7], while LD[7] (lsb) connects to IO[0].