Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-51
with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding
with LCSn negation
10.4.2.3.5 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose
some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank
is delayed by the number of clock cycles specified in Table 10-7 in addition to any existing bus turnaround
cycle. The final bus turnaround cycle is automatically inserted by the eLBC for reads, regardless of the
setting of ORn[EHTR].
Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
Figure 10-42. GPCM Read Followed by Write
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads)
LCLK
LA
LD
TA
LCSn
LOE
LBCTL
Address1 Address2
Read Data1
LCSy
Bus
Turnaround
Read Data2
LCLK
LA
LD
TA
LCS
n
LOE
LBCTL
Address1
LCSy
Bus
Turnaround
Address2
Extended
Hold
Read Data Write Data