Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-50 Freescale Semiconductor
When TRLX and CSNT are set in a write access, the LWE[0:1] strobe signals are negated one clock earlier
than in the normal case, as shown in Figure 10-39 and Figure 10-40. If ACS 00, LCSn is also negated
one clock earlier.
Figure 10-39. GPCM Relaxed Timing Write
(XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV = 4, 8)
Figure 10-40. GPCM Relaxed Timing Write
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8)
10.4.2.3.4 Output Enable (LOE) Timing
The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge of the
bus clock. LOE
asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with
LCSn (if XACS = 1 and ACS = 10 or ACS = 11). Accordingly, assertion of LOE can be delayed (along
LCLK
LA
LD
TA
LCS
n
LWEn
LOE
LBCTL
Address
Write Data
CSNT=1ACS=10
LCLK
LA
LD
TA
LCSn
LWEn
LOE
LBCTL
Address
Write Data
CSNT=1
SCY=1,TRLX=1