Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-49
Figure 10-37. GPCM Relaxed Timing Back-to-Back Reads
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)
Figure 10-38. GPCM Relaxed Timing Back-to-Back Writes
(XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8)
Bus
Turnaround
LCLK
LCS
n
LWEn
LA
LD
TA
LBCTL
LOE
Address1
Read Data
Extended
Hold Time
SCY=1,TRLX=1
Address2
ACS=10
ACS=11
LCLK
LA
LD
TA
LCSn
LWEn
LOE
LBCTL
Address1 Address2
Write Data1 Write Data2
ACS=10 ACS=11
ACS=10