Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-48 Freescale Semiconductor
example, when ACS = 00 and CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in
Figure 10-36. If LCRR[CLDIV] = 2, LWEn is negated coincident with LCSn.
1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWEn is affected
independent of ACS.
2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal
case provided that LCRR[CLDIV] = 4 or 8.
3. TRLX = 1 in conjunction with CSNT = 1, negates the LWEn 1+1/4 cycle earlier if
LCRR[CLKDIV] = 4 or 8.
If LCRR[CLKDIV] = 2, LCSn and LWEn are negated one cycle earlier if TRLX = 1.
For example, when ACS = 00, CSNT = 1 and TRLX = 0, LWEn is negated one quarter of a clock earlier
and LCSn is negated normally as shown in Figure 10-36.
10.4.2.3.3 Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
• An additional bus cycle is added between the address and control signals (but only if ACS is not
equal to 00).
• The number of wait states specified by SCY is doubled, providing up to 30 wait states.
• The extended hold time on read accesses (EHTR) is extended further.
•LCSn signals are negated one cycle earlier during writes (but only if ACS is not equal to 00).
•LWE[0:1] signals are negated one cycle earlier during writes.
Figure 10-37 and Figure 10-38 show relaxed timing read and write transactions. The effect of
LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to
the ACS = 11 case. The example in Figure 10-38 also shows address and data multiplexing on LD for a
pair of writes issued consecutively.