Information
Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-47
• Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1.
• Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1 and
ORn[TRLX] = 1.
The timing diagram in Figure 10-33 shows two chip-select assertion timings for the case
LCRR[CLKDIV] = 4 or 8. If LCRR[CLKDIV] = 2, LCSn asserts identically for ORn[ACS] = 10 or 11.
10.4.2.3.1 Programmable Wait State Configuration
The GPCM supports internal generation of transfer acknowledge. It allows between zero and 30 wait states
to be added to an access by programming ORn[SCY] and ORn[TRLX]. Internal generation of transfer
acknowledge is enabled if ORn[SETA] = 0. If LGTA is asserted externally two bus clock cycles or more
before the wait state counter has expired (to allow for synchronization latency), the current memory cycle
is terminated by LGTA; otherwise it is terminated by the expiration of the wait state counter. Regardless
of the setting of ORn[SETA], wait states prolong the assertion duration of both LOE and LWEn in the same
manner. When TRLX = 1, the number of wait states inserted by the memory controller is doubled from
ORn[SCY] cycles to 2×ORn[SCY] cycles, allowing a maximum of 30 wait states.
10.4.2.3.2 Chip-Select and Write Enable Negation Timing
Figure 10-32 shows a basic connection between the local bus and a static memory device. In this case,
LCSn is connected directly to CE of the memory device. The LWE[0:1] signals are connected to the
respective WE[1:0] signals on the memory device where each LWE[0:1] signal corresponds to a different
data byte.
Figure 10-36. GPCM Basic Write Timing
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 2, 4, 8)
The strobes for the transaction are supplied by LOE or LWEn, depending on the transaction
direction—read or write (write case shown in the figure). ORn[CSNT], along with ORn[TRLX], control
the timing for the appropriate strobe negation in write cycles. When this attribute is asserted, the strobe is
negated one quarter of a clock before the normal case provided that LCRR[CLKDIV] = 2, 4, or 8. For
LCLK
LA
LD
LOE
TA
LCS
n
Valid Address
Write Data
LWEn
CSNT=1
SCY=1