Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-46 Freescale Semiconductor
10.4.2.3 Chip-Select Assertion Timing
The banks selected to work with the GPCM support an option to drive the LCSn signal with different
timings (with respect to the external address/data bus). LCS
n can be driven in any of the following ways:
• One quarter of a clock cycle later (for LCRR[CLKDIV] = 4, 8).
• One half of a clock cycle later (for LCRR[CLKDIV] = 2, 4, or 8).
• One clock cycle later (for LCRR[CLKDIV] = 4), when ORn[XACS] = 1.
00101 ¼
(½)
1½+SCY 1 0 1¾+SCY
(1½+SCY)
00111 ½ 1¼+SCY
(1+SCY)
101¾+SCY
(1½+SCY)
0 1 00 1 0 2+SCY 1 ¼
(0)
2+SCY
0 1 10 1 1 ¾+SCY
(½+SCY)
101¾+SCY
(1½+SCY)
0 1 11 1 2 ¾+SCY
(½+SCY)
202¾+SCY
(2½+SCY)
1 0 00 0 0 2+2×SCY 1 0 2+2×SCY
10100 1¼
(1½)
1¾+2×SCY
(2+2×SCY)
203+2×SCY
1 0 11 0 1½ 1½+2×SCY 2 0 3+2×SCY
1 1 00 0 0 2+2×SCY 1 0 2+2×SCY
1 1 10 0 2 1+2×SCY 2 0 3+2×SCY
1 1 11 0 3 1+2×SCY 3 0 4+2×SCY
1 0 00 1 0 3+2×SCY 1 1¼
(1)
3+2×SCY
10101 1¼
(1½)
1½+2×SCY 2 0 2¾+2×SCY
(2½+2×SCY)
1 0 11 1 1½ 1¼+2×SCY
(1+2×SCY)
2 0 2¾+2×SCY
(2½+2×SCY)
1 1 00 1 0 3+2×SCY 1 1¼
(1)
3+2×SCY
1 1 10 1 2 ¾+2×SCY
(½+2×SCY)
2 0 2¾+2×SCY
(2½+2×SCY)
1 1 11 1 3 ¾+2×SCY
(½+2×SCY)
3 0 3¾+2×SCY
(3½+2×SCY)
1
Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.
Table 10-33. GPCM Write Control Signal Timing (continued)
Option Register Attributes Signal Timing (LCLK clock cycles)
1
TRLX XACS ACS CSNT t
AWCS
t
CSWP
t
AWE
t
WEN
t
WC