Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-45
10.4.2.2 GPCM Write Signal Timing
The basic GPCM write timing parameters that may be set by the ORn attributes are shown in Figure 10-35.
The write access cycle commences upon latching of the memory address, and concludes when LCSn
returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data bus. Write
data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high before the
end of the write access to provide additional hold time for the external memory.
Figure 10-35. GPCM General Write Timing Parameters
Table 10-33 lists the signal timing parameters for a GPCM write access as the option register attributes are
varied.
Table 10-33. GPCM Write Control Signal Timing
Option Register Attributes Signal Timing (LCLK clock cycles)
1
TRLX XACS ACS CSNT t
AWCS
t
CSWP
t
AWE
t
WEN
t
WC
0 0 00 0 0 2+SCY 1 0 2+SCY
00100 ¼
(½)
1¾+SCY
(2+SCY)
102+SCY
0 0 11 0 ½ 1½+SCY 1 0 2+SCY
0 1 00 0 0 2+SCY 1 0 2+SCY
0 1 10 0 1 1+SCY 1 0 2+SCY
0 1 11 0 2 1+SCY 2 0 3+SCY
0 0 00 1 0 2+SCY 1 ¼
(0)
2+SCY
LCLK
LA
LD
LWE
LBCTL
TA
LCSn
Valid Address
Write Data
t
CSWP
t
AWE
t
WEN
t
WC
Notes:
t
WC
= Write cycle time.
t
AWCS
= Address valid to write chip-select time.
t
AWE
= Address valid to write enable time.
t
CSWP
= Write chip-select assertion period.
t
WEN
= Write enable negated time write
chip-select negation time.
t
AWCS