Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xlii Freescale Semiconductor
Tables
Table
Number Title
Page
Number
9-38 DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self
Refresh Disabled .............................................................................................................. 9-43
9-39 DDR2 Address Multiplexing for 16-Bit Data Bus................................................................ 9-44
9-40 Example of Address Multiplexing for 32-Bit Data Bus Interleaving between
Two Banks with Partial Array Self Refresh Disabled...................................................... 9-45
9-41 DDR SDRAM Command Table............................................................................................ 9-46
9-42 DDR SDRAM Interface Timing Intervals ............................................................................ 9-47
9-43 DDR SDRAM Power-Saving Modes Refresh Configuration............................................... 9-55
9-44 Memory Controller–Data Beat Ordering .............................................................................. 9-57
9-45 DDR SDRAM ECC Syndrome Encoding ............................................................................ 9-58
9-46 DDR SDRAM ECC Syndrome Encoding (Check Bits) ....................................................... 9-59
9-47 Memory Controller Errors ....................................................................................................9-60
9-48 Memory Interface Configuration Register Initialization Parameters.................................... 9-61
10-1 Signal Properties—Summary................................................................................................ 10-4
10-2 Enhanced Local Bus Controller Detailed Signal Descriptions ............................................. 10-5
10-3 Enhanced Local Bus Controller Registers ............................................................................ 10-7
10-4 BRn Field Descriptions....................................................................................................... 10-10
10-5 Reset value of OR0 Register............................................................................................... 10-11
10-6 Memory Bank Sizes in Relation to Address Mask ............................................................. 10-11
10-7 ORn—GPCM Field Descriptions ....................................................................................... 10-12
10-8 ORn—FCM Field Descriptions .......................................................................................... 10-15
10-9 ORn—UPM Field Descriptions.......................................................................................... 10-17
10-10 MAR Field Descriptions ..................................................................................................... 10-18
10-11 MxMR Field Descriptions................................................................................................... 10-19
10-12 MRTPR Field Descriptions................................................................................................. 10-21
10-13 MDR Field Description....................................................................................................... 10-22
10-14 LSOR Field Description...................................................................................................... 10-23
10-15 LURT Field Descriptions.................................................................................................... 10-24
10-16 LTESR Field Descriptions .................................................................................................. 10-25
10-17 LTEDR Field Descriptions.................................................................................................. 10-26
10-18 LTEIR Field Descriptions ................................................................................................... 10-27
10-19 LTEATR Field Descriptions................................................................................................ 10-28
10-20 LTEAR Field Descriptions.................................................................................................. 10-29
10-21
LTECCR Field Descriptions ............................................................................................... 10-29
10-22 LBCR Field Descriptions.................................................................................................... 10-30
10-23 LCRR Field Descriptions.................................................................................................... 10-32
10-24 FMR Field Descriptions...................................................................................................... 10-33
10-25 FIR Field Descriptions........................................................................................................ 10-35
10-26 FCR Field Descriptions....................................................................................................... 10-35
10-27 FBAR Field Descriptions.................................................................................................... 10-36
10-28 FPAR Field Descriptions, Small Page Device (ORx[PGS] = 0)......................................... 10-37