Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-43
memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR
and SETA fields.
Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)
10.4.2.1 GPCM Read Signal Timing
The basic GPCM read timing parameters that may be set by the ORn attributes are shown in Figure 10-34.
The read access cycle commences upon latching of the memory address and concludes when LBCTL
returns high to turn the local bus around for a subsequent address phase. Read data is captured by eLBC
on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases before the end of the
read access to provide additional hold time for the external memory.
Figure 10-34. GPCM General Read Timing Parameters
LCLK
LD
LA
TA
LCSn
LOE
Read Data
Valid Address
ACS=10 ACS=11
LCLK
LD
LA
LOE
LBCTL
Read Data
TA
LCS
n
Valid Address
t
CSRP
t
AOE
t
RC
t
OEN
Notes:
t
RC
= Read cycle time.
t
ARCS
= Address valid to read chip-select time.
t
ARCS
t
AOE
= Address valid to output enable time.
t
CSRP
= Read chip-select assertion period.
t
OEN
= Output enable negated time.