Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-42 Freescale Semiconductor
are pending, LBCTL is asserted (high) one bus clock cycle before the next transaction starts to allow a
whole bus cycle for the bus to turn around before the next address is driven.
10.4.1.4 Bus Monitor
A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable (user defined)
period. When a transaction starts, the bus monitor starts counting down from the time-out value
(LBCR[BMT] × LBCR[BMTPS]) until a data beat is acknowledged on the bus. It then reloads the time-out
value and resumes the countdown until the data tenure completes and then idles if there is no pending
transaction. Setting LTEDR[BMD] disables bus monitor error checking (that is, the LTESR[BM] bit is not
set by a bus monitor time-out); however, the bus monitor is still active and can generate a UPM exception
(as noted in Section 10.4.4.1.4, “Exception Requests,”) or terminate a GPCM access.
It is very important to ensure that the value of LBCR[BMT] is not set too low; otherwise spurious bus
time-outs may occur during normal operation—resulting in incomplete data transfers. Accordingly, the
time-out value represented by the LBCR[BMT], LBCR[BMTPS] pair must not be set below 40 bus cycles
for time-out under any circumstances.
10.4.2 General-Purpose Chip-Select Machine (GPCM)
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BRn and
ORn.
Figure 10-32 shows a simple connection between an 8-bit port size SRAM device and the eLBC in GPCM
mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
Figure 10-32. Enhanced Local Bus to GPCM Device Interface
Note that LWE0 is used for LD[0:7] and LWE1 is used for LD[8:15] for an 8-bit access to a 16-bit device.
Figure 10-33 shows LCS
as defined by the setup time required between the address lines and CE. The user
can configure ORn[ACS] to specify LCS
to meet this requirement. Generally, the attributes for the
CE
OE
WE
Data[7:0]
Memory/Peripheral
LWE0
LOE
LCSn
LD[0:7]
eLBC in GPCM
Mode
LA[6:25] A[19:0]