Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-41
Figure 10-30. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0)
10.4.1.2 Data Transfer Acknowledge (TA)
The three memory controllers in the eLBC generate an internal transfer acknowledge signal, TA, to allow
data on LD to be either sampled (for reads) or changed (on writes). The data sampling/data change always
occurs at the end of the bus cycle in which the eLBC asserts TA internally. In eLBC debug mode, TA is
also visible externally on the LDVAL pin. The GPCM controller automatically generates TA according to
the timing parameters programmed for them in the option and mode registers; FCM generates TA
whenever data read and write instructions are executed out of register FIR; a UPM generates TA only when
a UPM pattern has the UTA RAM word bit set. Figure 10-31 shows TA (internal), and LCSn.
Figure 10-31. Basic eLBC Bus Cycle with TA, and LCSn
10.4.1.3 Data Buffer Control (LBCTL)
The memory controller provides a data buffer control signal for the local bus (LBCTL). This signal is
activated when a GPCM-, FCM-, or UPM-controlled bank is accessed. LBCTL can be disabled by setting
ORn[BCTLD]. LBCTL can be further configured by LBCR[BCTLC] to act as an extra LWE
or an extra
LOE
signal when in GPCM mode.
If LBCTL is configured as a data buffer control (LBCR[BCTLC] = 00), the signal is asserted (high) on the
rising edge of the bus clock on the first cycle of the memory controller operation. If the access is a write,
LBCTL remains high for the whole duration. However, if the access is a read, LBCTL is negated (low)
with the assertion of LCS
so that the memory device is able to drive the bus. If back-to-back read accesses
LCLK
LCS
LWE
LA[0:25]
LD[0:15]
5420 5421 5422 5423
D[B0] D[B1] D[B2] D[B3]
543C 543D 543E
DB[28] D[B29] D[B30]
543F
D[B31]
Note: All address and signal values are shown in hexadecimal.
D[Bk] = k
th
of 32 data bytes.
LCLK
LA
LCSn
LD
TA
Address
Data