Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-40 Freescale Semiconductor
Figure 10-29. Basic Operation of Memory Controllers in the eLBC
Each memory bank (chip select) can be assigned to any of these three types of machines through the
machine select bits of the base register for that bank (BRn[MSEL]), as illustrated in Figure 10-29. If a bank
match occurs, the corresponding machine (GPCM, FCM, or UPM) then takes ownership of the external
signals that control the access and maintains control until the transaction ends.
10.4.1 Basic Architecture
The following subsections describe the basic architecture of the eLBC.
10.4.1.1 Address and Address Space Checking
The defined base addresses are written to the BRn registers, while the corresponding address masks are
written to the ORn registers. Each time a local bus access is requested, the internal transaction address is
compared with each bank. Addresses are decoded by comparing the 17 MSBs of the address, masked by
ORn[AM], with the base address for each bank (BRn[BA]). If a match is found on a memory controller
bank, the attributes defined in the BRn and ORn for that bank are used to control the memory access. If a
match is found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank
0 has priority over bank 1).
To illustrate how a large transaction is handled by the eLBC, Figure 10-30 shows eLBC signals for the
GPCM performing a 32-byte write starting at address 0x5420.
Address
Comparator
Bank Select
FCM buffer
GPCM
MSEL
Field
Signals Timing Generator
Internal Memory Access Request Select
32-bit System
External Signals
Address
32-bit Physical
RAM Address (A)
UPM A/B/C
FCM
RAM