Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-38 Freescale Semiconductor
10.3.1.22 Flash Byte Count Register (FBCR)
The local bus Flash byte count register (FBCR), shown in Figure 10-27, defines the size of FCM block
transfers for reads and writes to the NAND Flash EEPROM.
Table 10-30 describes FBCR fields.
10.3.1.23 Flash ECC Blockn Register (FECC0–FECC3)
The local bus flash ECC blockn register (FECCn), shown in Figure 10-28, specifies the ECC value
calculated during writes or reads by eLBC. It can be used for verify after write feature in software. Note
that the valid bit sets before the command completion event and hence the correct ECC could be read
before actual completion of writes/reads.
Offset 0x0_50F4 Access: Read/Write
0192031
R
—BC
W
Figure 10-27. Flash Byte Count Register
Table 10-30. FBCR Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 BC Byte count determines how many bytes are transferred by the FCM during data read (RB) or data write
(WB) opcodes.
The first byte accessed in the NAND Flash EEPROM is located by the FPAR register, and successive
bytes are transferred until either BC bytes have been counted, or the end of the spare region of the
currently addressed Flash page has been reached.
If BC = 0, an entire Flash page and its spare region will be transferred by FCM, in which case
FPAR[MS] and FPAR[CI] are treated as zero regardless of their values. BC = 0 is the only setting that
permits FCM to generate and check ECC.
Offset FECC0: 0x0_5100
FECC1: 0x0_5104
FECC2: 0x0_5108
FECC3: 0x0_510C
Access: Read Only
01 78 31
RV
—
ECC
W
Reset All zeros
Figure 10-28. Flash ECC Blockn Register (FECC0–FECC3)