Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-36 Freescale Semiconductor
10.3.1.20 Flash Block Address Register (FBAR)
The local bus Flash block address register (FBAR), shown in Figure 10-24, locates the NAND Flash
block index for the page currently accessed.
Table 10-27 describes FBAR fields.
10.3.1.21 Flash Page Address Register (FPAR)
The local bus Flash page address register (FPAR), shown in Figure 10-25 and Figure 10-26, locates the
current NAND Flash page in both the external NAND Flash device and FCM buffer RAM.
Offset 0x0_50EC Access: Read/Write
078 31
R
—BLK
W
Reset All zeros
Figure 10-24. Flash Block Address Register
Table 10-27. FBAR Field Descriptions
Bits Name Description
0–7 — Reserved
8–31 BLK Flash block address. The size of the NAND Flash, as configured in ORn[PGS] and FMR[AL],
determines the number of bits of BLK that are issued to the EEPROM during block address phases.
Offset 0x0_50F0 Access: Read/Write
0161721222331
R
—
PI
MS CI
W
Reset All zeros
Figure 10-25. Flash Page Address Register, Small Page Device (ORx[PGS] = 0)
Offset 0x0_50F0 Access: Read/Write
0 1314 192021 31
R
—
PI
MS CI
W
Reset All zeros
Figure 10-26. Flash Page Address Register, Large Page Device (ORx[PGS] = 1)