Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-33
Table 10-24 describes FMR fields.
Table 10-24. FMR Field Descriptions
Bits Name Description
0–15 — Reserved
16–19 CWTO Command wait time-out. For FCM commands that wait on LFRB
being sampled high (CW0, CW1,
RBW and RSW), FCM pauses execution of the instruction sequence until either LFRB is sampled high,
or a timer controlled by CTO expires, whichever occurs first. The time-out in the latter case is:
0000 256 cycles of LCLK0
0001 512 cycles of LCLK0
0010 1024 cycles of LCLK0
0011 2048 cycles of LCLK0
0100 4096 cycles of LCLK0
0101 8192 cycles of LCLK0
0110 16,384 cycles of LCLK0
0111 32,768 cycles of LCLK0
1000 65,536 cycles of LCLK0
1001 131,072 cycles of LCLK0
1010 262,144 cycles of LCLK0
1011 524,288 cycles of LCLK0
1100 1,048,576 cycles of LCLK0
1101 2,097,152 cycles of LCLK0
1110 4,194,304 cycles of LCLK0
1111 8,388,608 cycles of LCLK0
20 BOOT Flash auto-boot load mode. During system boot from NAND Flash EEPROM, this bit remains set to
alter the use of the FCM buffer RAM. Software should clear BOOT once FCM is to be restored to
normal operation. Setting BOOT without auto-boot in progress only alters the mapping of the buffer
RAM.
0 FCM is operating in normal functional mode, with an 8 Kbyte FCM buffer RAM.
1 eLBC has been configured—either from reset or by a special operation OP = 01—to auto-load a
4-Kbyte boot block into the FCM buffer RAM, which maps only the 4 Kbytes of NAND flash main
data region comprising the boot block. Any access to the buffer RAM is delayed until the entire boot
block has been loaded.
21–22 — Reserved
23 ECCM ECC mode. When hardware checking and/or generation of error correcting codes (ECC) is enabled
(that is, when BRn[DECC] is 01 or 10, and full page transfers are specified with FBCR[BC] = 0), ECCM
sets the ECC block size and position of the ECC code word(s) in the NAND Flash spare region for both
checking and generation functions. The format of the ECC code word conforms with the
Samsung/Toshiba spare region assignment specifications.
0 ECC is checked/calculated over 512-Byte blocks. A 24-bit ECC is assigned to spare region bytes at
offsets (N×16)+6 through (N×16)+8 for spare region N, N = 0–3.
1 ECC is checked/calculated over 512-Byte blocks. A 24-bit ECC is assigned to spare region bytes at
offsets (N×16)+8 through (N×16)+10 for spare region N, N = 0–3.
24–25 — Reserved