Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-32 Freescale Semiconductor
Table 10-23 describes LCRR fields.
10.3.1.17 Flash Mode Register (FMR)
The local bus Flash mode register (FMR), shown in Figure 10-21, controls global operation of the FCM.
Table 10-23. LCRR Field Descriptions
Bits Name Description
0 PBYP PLL bypass. This bit should be set when using low bus clock frequencies (66 MHz or lower).
When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle.
0 The PLL is enabled.
1 The PLL is bypassed. (Default: This device supports PLL Bypass Mode only.)
1–26 — Reserved
Although bit 14 and 15 are reserved, they can be still programmed with the following to provide
additional delay to LCLK:
00 4
01 1
10 2
11 3
27–31 CLKDIV System clock divider. Sets the frequency ratio between the system clock and the local bus clock.
The system clock is equivalent to csb_clk or twice csb_clk (if RCWL[LBCM] is set). Only the
values shown below are allowed.
Note: It is critical that no transactions are being executed via the local bus while CLKDIV is being
modified. As such, prior to modification, the user must ensure that code is not executing
out of the local bus. Once LCRR[CLKDIV] is written, the register should be read, and then
an isync should be executed.
00000–00001 Reserved
00010 2
00011 Reserved
00100 4
00101–00111 Reserved
01000 8
01001–11111 Reserved
Offset 0x0_50E0 Access: Read/Write
0 1516 19 20 2122 23 2425262728293031
R
— CWTO BOOT — ECCM — AL — OP
W
Reset0 000000000000000 0 0 0 0 R
1
1
Bit R (field BOOT) is set if power-on-reset configuration selects FCM as the boot ROM target.
00 0 00000000
Figure 10-21. Flash Mode Register