Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-31
10.3.1.16 Clock Ratio Register (LCRR)
The clock ratio register, shown in Figure 10-20, sets the system clock to eLBC bus frequency ratio. It also
provides configuration bits for extra delay cycles for address and control signals.
NOTE
For proper operation of the system, it is required that this register setting
will not be altered while local bus memories or devices are being accessed.
Special care needs to be taken when running instructions from an eLBC
memory.
24–27 — Reserved
28–31 BMTPS Bus monitor timer prescale. Defines the multiplier, PS, to scale LBCR[BMT] for determining bus time-outs.
0000 PS = 8
0001 PS = 16
0010 PS = 32
0011 PS = 64
0100 PS = 128
0101 PS = 256
0110 PS = 512
0111 PS = 1024
1000 PS = 2048
1001 PS = 4096
1010 PS = 8192
1011 PS = 16,384
1100 PS = 32,768
1101 PS = 65,536
1110 PS = 131,072
1111 PS = 262,144
Offset 0x0_50D4 Access: Read/Write
01 26 27 30 31
R
PBYP —
CLKDIV
W
Reset 1 000000000000 000000000000000nn00
Figure 10-20. Clock Ratio Register (LCRR)
Table 10-22. LBCR Field Descriptions (continued)
Bits Name Description