Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-30 Freescale Semiconductor
10.3.1.15 Local Bus Configuration Register (LBCR)
The local bus configuration register (LBCR) is shown in Figure 10-19.
Table 10-22 describes LBCR fields.
Offset 0x0_50D0 Access: Read/Write
01 7891011 15
R
LDIS — BCTLC —
W
Reset0000000000000100
16 23 24 27 28 31
R
BMT — BMTPS
W
Reset All zeros
Figure 10-19. Local Bus Configuration Register
Table 10-22. LBCR Field Descriptions
Bits Name Description
0 LDIS Local bus disable
0 Local bus is enabled.
1 Local bus is disabled. No internal transactions will be acknowledged.
1–7 — Reserved
8–9 BCTLC Defines the use of LBCTL
00 LBCTL is used as W/R
control for GPCM or UPM accesses (buffer control).
01 LBCTL is used as LOE for GPCM accesses only.
10 LBCTL is used as LWE
for GPCM accesses only.
11 Reserved.
10 — Reserved
11–15 — Reserved.
Note: Reads to bit 13 return 1. During writes, it is recommended to write 1 to bit 13.
16–23 BMT Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the
maximum count of bus clock cycles. For non-zero values of BMT, the number of LCLK clock cycles to count
down before a time-out error is generated is given by:
bus cycles = BMT × PS, where PS is set according to LBCR[BMTPS].
The value of BMT × PS must not be less than 40 bus cycles for reliable operation.