Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 10-29
10.3.1.13 Transfer Error Address Register (LTEAR)
The transfer error address register (LTEAR) captures the address of a transaction that caused an
error/event. The transfer error address register (LTEAR) is shown in Figure 10-17.
Table 10-20 describes LTEAR fields.
10.3.1.14 Transfer Error ECC Register (LTECCR)
The transfer error ECC register (LTECCR) captures single bit and multibit errors per 512-byte sector in
FCM mode. LTECCR, shown in Figure 10-18, is a write-1-to-clear register. Write operations can clear but
not set bits. It captures the errors during full page read transfers on FCM command completion event,
provided ECC check is enabled in BRx[DECC].
Offset 0x0_50C0 Access: Read/Write
0 31
R
A
W
Reset All zeros
Figure 10-17. Transfer Error Address Register (LTEAR)
Table 10-20. LTEAR Field Descriptions
Bits Name Description
0–31 A Transaction address for the error. For GPCM and UPM, holds the 32-bit address of the transaction resulting
in an error. For FCM, this register is undefined.
Offset 0x0_50C4 Access: w1c
011121516272831
R
— SBCE — MBUE
W
Reset All zeros
Figure 10-18. Transfer Error ECC Register (LTECCR)
Table 10-21. LTECCR Field Descriptions
Bits Name Description
0–11 — Reserved
12–15 SBCE Single bit correctable error
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had a single bit correctable ECC error on read (bit 12 represents block 0, the first
512 bytes of a page; if ORx[PGS] = 0, bits 13–15 are always 0).
16–27 — Reserved
28–31 MBUE Multi bit uncorrectable error
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had an uncorrectable ECC error on read (bit 28 represents block 0, the first 512
bytes of a page; if ORx[PGS] = 0, bits 29–31 are always 0).