Information

Enhanced Local Bus Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
10-28 Freescale Semiconductor
10.3.1.12 Transfer Error Attributes Register (LTEATR)
The transfer error attributes register (LTEATR) captures source attributes of an error/event. Figure 10-16
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow LTESR,
LTEATR, and LTEAR to update following any subsequent events/errors.
Table 10-19 describes LTEATR fields.
30 UCCI UPM Run pattern command completion Event interrupt enable.
0 UPM Run pattern command completion reporting is disabled.
1 UPM Run pattern command completion reporting is enabled.
31 CCI FCM command completion Event interrupt enable.
0 Command completion reporting is disabled.
1 Command completion reporting is enabled.
Offset 0x0_50BC Access: Read/Write
0 2 3 4 10 11 15 16 19 20 23 24 30 31
R
—RWB —
SRCID
PB BNK — V
W
Reset All zeros
Figure 10-16. Transfer Error Attributes Register (LTEATR)
Table 10-19. LTEATR Field Descriptions
Bits Name Description
0–2 — Reserved
3 RWB Transaction type for the error:
0 The transaction for the error was a write transaction.
1 The transaction for the error was a read transaction.
4–10 — Reserved
11–15 SRCID Captures the source of the transaction when this information is provided on the internal interface to the eLBC.
For more information, see Tabl e 6- 8 in Section 6.2.7, “Arbiter Event Attributes Register (AEATR).”
16–19 PB Error on block for FCM. For FCM, there are at most four 512-byte page blocks (for a large page device)
checked by ECC. A bit is set for the 512-byte block that had an uncorrectable ECC error on read (bit 16
represents block 0, the first 512 bytes of a page; if ORx[PGS] = 0, bits 17–19 are always 0).
20–23 BNK Memory controller bank. There is one error status bit per memory controller bank (bit 20 represents bank 0).
A bit is set for the local bus memory controller bank that had an error.
24–30 — Reserved
31 V Error attribute capture is valid. Indicates that the captured error information is valid.
0 Captured error attributes and address are not valid.
1 Captured error attributes and address are valid.
Table 10-18. LTEIR Field Descriptions (continued)
Bits Name Description